`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:09:41 09/29/2011
// Design Name:   LCD_Fibonauchi_TEST
// Module Name:   C:/Users/Chase/16bitcpu/fibonacci_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: LCD_Fibonauchi_TEST
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fibonacci_test;

	// Inputs
	reg CLK;
	reg reset;

	// Outputs
	wire [11:8] SF_D;
	wire LCD_E;
	wire LCD_RS;
	wire LCD_RW;

	// Instantiate the Unit Under Test (UUT)
	LCD_Fibonauchi_TEST uut (
		.CLK(CLK), 
		.reset(reset), 
		.SF_D(SF_D), 
		.LCD_E(LCD_E), 
		.LCD_RS(LCD_RS), 
		.LCD_RW(LCD_RW)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;
		#100;
		reset = 0;
		// Add stimulus here

	end
      
		always begin
		#5 CLK = ~CLK;
		end
		
endmodule

